Design of Low Power High Speed Hybrid Full Adder

In this paper, a proposed 1-bit hybrid full adder design employing both transmission gate logic and complementary metal– oxide–semiconductor (CMOS) logic is reported. The design is implemented for 1-bit Ripple Carry Adder and then is extended for 64-bit Ripple Carry Adder. The circuit is implemented using Mentor Graphics tools 130nm technology. The performance parameters such as delay, area, total power dissipation and power delay product (PDP) were compared with the existing designs such as Conventional CMOS full adder (CMOS), Complementary pass transistor logic (CPL), Transmission function full adder (TFA), HPSC full adder and Low Energy HPSC full adder with proposed 1-bit hybrid full adder and modified 1-bit hybrid full adder. For 1V supply at 130-nm technology, the average power consumption is found to be extremely low with moderately low delay resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. The design is further extended for 32-Bit and 64-bit full adder also, and is found to be working efficiently with less delay and less power dissipation at 130-nm technology for 1V Supply voltage. In comparison with the previous full adder designs, the hybrid adder offers significant improvement in terms of power, area and speed.